The present invention relates to devices for carrying out operations in a computer and, more particularly, to central processing unit intended to process operands represented in a system of residual classes (see the "Residue Code System", U.S. Pat. No. 3,602,704).
It is a generally recognized fact that the performance of a computer incorporating a processor which operates in the system or residual classes is markedly improved.
However, in order to develop a universal computer based on a processor which operates in the system of residual classes, it is necessary to perform a complete set of operations without any constraint as regards the initial operands.
A computer processor, which is intended for operands represented in the system of residual classes (cf. U.S.S.R. Inventor's Certificate No. 419,891 of Apr. 6, 1972), is known which comprises first and second operand registers with signs, their inputs being connected to first and second operand buses; a modular arithmetic unit whose inputs are connected to outputs of the first and second operand registers and to a control bus; an analysis system whose inputs are connected to outputs of the first and second operand registers, the control bus and an output of the modular arithmetic unit, one output of the analysis system being connected to an input of the modular arithmetic unit; and a result register with a sign, its input being connected to the output of the modular arithmetic unit, its second input being connected to a second output of the analysis system, its output being connected via a result output circuit to a result bus, an input of the result output circuit being connected to a third output of the analysis system.
The analysis system includes a checking circuit and a control circuit, first outputs of said circuits being connected via an OR gate to the second output of the analysis system, a second output of the checking circuit being connected to the third output of the analysis system.
The processor review operates as follows. During the first stage of operation, the first and second operand registers memorize the operands with signs.
Information on the signs of the operands is sent to the analysis system.
By a control signal indicating the type of operation to be performed, which may be any rational operation of multiplication, addition and subtraction, the modular arithmetic unit determines the result, which is stored in the result register, and the analysis system determines the sign of the result, which is stored in the sign digit of the result register. By a signal from the third output of the analysis system, the result is transmitted via the result output bus to the result bus.
A major disadvantage of the processor under review is the absence of units for multiplying and dividing arbitrarily chosen numbers.
In addition, the analysis system includes an analysis circuit which processes information in a strictly sequential order (the operation of "nullivization" see U.S. Pat. No. 3,602,704), which considerably reduces the operating speed of the processor under review and other processors of similar types.